MaPnet: A Three Dimensional Fabric for Reliable Multi-core Processors
نویسندگان
چکیده
Technological trends into the nanometer regime have led to significantly higher failure rates. Consequently, high reliability and fault tolerance are now getting more emphasis. We are attempting to solve these issues of reliability and tolerance on a simple pipeline, generally used in many-core designs and GPUs. StageNet, which is fine-grained reconfigurable pipeline design in a multi-core processor, is our baseline design, has been proposed for multiprocessor fault tolerance [1]. However, original StageNet design results in large performance degradation and poor scalability because of limitation of 2D design. In this paper, we propose 3D reconfigurable pipeline design, named MaPnet. Our key idea is to reduce routing distance and complexity by using Through Silicon Vias (TSVs). Our 3D design enables us to minimize interconnect delay and thus increase the number of cores without large performance degradation. In order to maximize the benefit of TSVs, we introduced an extra delay cycle in the pipeline, thus retaining the original operating frequency instead of lowering it. The interconnection delay and extra delay cycles are been estimated based on the physical design and layout of our RTL code. In addition, SPICE simulation is performed to calculate accurate interconnect delay in the layouts. Our evaluation with various test cases shows that the proposed 3D design has 16.3% of IPC improvement over 2D design on an average in the same failure scenarios. Keywords—Fault tolerance, reliability, chip multi-processor, virtual pipeline.
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تاریخ انتشار 2015